1. Field of the Invention
The present invention generally relates to a fail-free method and device for storing and reading a chunk of information in a non-volatile memory device. More specifically, a NAND flash memory device and method may use its page region having broken bits for correctly storing information with a reduced page size, and an error-free device and method for storing data may use a rule based on a minimum bit set that is chosen using a maximum number of bits failed per data and that is coherent with the data size used in the memory.
2. Description of the Related Art
Each NAND flash memory device usually needs a normal memory to store normal information used by the device user and an additional memory to store configuration information for accessing the memory, such as trimming internal parameters, a bad block address table, and a column fail address table. The configuration information usually is stored at the conclusion of the validation tests, before the memory chip reaches the market.
Some conventional mechanisms for such configuration information storage may use a content addressable memory (CAM) or may use fuses in flash devices. However, the CAM or the fuses may be different in structure from a core memory and may be operated for write, read, and erase differently from the core memory.
A conventional mechanism for such normal information storage may use an EEPROM (Electrically Erasable Programmable Read-Only Memory) to store the normal information. This conventional mechanism may use three EEPROMs such that an EEPROM are cloned three times in order to store reliably the information by storing the same information, and this also may use an analog circuit that makes, during the read phase, a majority check (2 versus 1) to discriminate the correct information if, during the device's life, some bit in the EEPROM fails. However, this conventinal mechanism does not disclose to reuse the memory having the broken cells, and does not disclose a specific implemention for a NAND flash memory device, especially using its page region.
Conventionally, it is not possible to use a row NAND page (memory area) to store information when there are columns broken in the row NAND page. Such row page having a broken cell cannot be used for storing correctly data in the conventional device.
Moreover, there is a failed bit correction mechanism such as a redundancy system using a failed address table. However, the failure repair capacity of this mechanism is limited. Especially, a NAND device can be validated only if there are a small number of broken columns and only a few bits fail per byte or word, as detected during testing of the device.